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20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373
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13 - 7
13
HMC920LP5E
v07.1013
ACTIVE BIAS CONTROLLER
Pin Descriptions
Pin Number
Function
Description
Interface Schematic
1, 2
Vdd1
Bias supply Pins. Connect supply voltage
to all these pins with appropriate filtering. Vdd1 supply
 voltage should be same as Vdd2.
3
VDIG
3.5V LDO output for internal use. Output capability <30mA.
Is not recommended for external use.
4
VDIGFB
Feedback node for VDIG LDO. Should be left floating for
regular operation.
5
PORCAP
External capacitor for power-on-reset signal. 47pF to
GND is needed. If longer POR duration is needed, can be
increased.
10
ALMSET
A resistor to ground is needed. The value of the resistor
determines the alarm delay duration. The value of the
resistor can be chosen between 10K and 10M.
12
FIXBIAS
A high precision (e.g. 0.5%, ?5 ppm TCR) 10K resistor
to ground is needed. Variance in the resistance will cause
deviation in the bias current.
6
BGCAP
External capacitor of bandgap output. Connect a
0.1uF or greater low ESR ceramic capacitor to GND.
7
EN
Enable pin. System is enabled when Ven is HIGH (3.5V). IF
left floating, Ven defaults to HIGH (enabled).
9
ALMTRG
Dummy alarm trigger signal to create test alarm when
taken HIGH (3.5V). Defaults to LOW (GND) when left
foating.
8
CURALM
Over/under current alarm
(Generates an active HIGH signal).
24
TRGOUT
Trigger out signal. Generates a HIGH (3.5V) signal when
the active bias system stabilizes. This signal can be
used to trigger next device (ENABLE) if more than one
HMC920LP5E is used in a daisy chain.
31
VddALM
Generates an active LOW signal if Vdd1 drops below 3.5V.
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